1. Field of the Invention
This invention relates to a semiconductor device having a semiconductor chip suitable for multi-chip package and a method of setting the capacity of an input pin for the semiconductor chip.
2. Description of the Related Art
Japanese Patent Application Number 10-321742 (hereinafter “related art”) describes that although a single chip package having only one chip per package has been a main stream in the field of DRAM, a multi-chip package having a plurality of chips per package has been developed recently to meet the requirements of a large capacity DRAM.
The related art proposed that in a double mounted type semiconductor device, an electrostatic protection circuit was provided in either a single semiconductor chip or two decentralized semiconductor chips.
The input pin capacity of a DRAM is specified that, for example, the maximum value is 5 PF and the minimum capacity is 2.5 PF. The input pin capacity consists of the package capacity that is determined according to the factors of a package and the chip capacity that is determined according to the factors of chips.
Since the package capacity is more difficult to change than the chip capacity, the related art proposed to adjust the chip capacity to meet the specifications.
FIG. 14 shows a conventional input circuit of a semiconductor chip. N-channel MOS transistors are used in the related art; however, CMOS transistors are used in FIG. 14 for convenience of comparison with the present invention.
The input circuit comprises an electrostatic protection element 1, an input pad 2, and a wiring 3. The electrostatic protection element 1 is a capacitor of CMOS transistors in which a P-channel MOS transistor Pch and an N-channel MOS transistor Nch are connected to each other.
The electrostatic protection element 1 is provided so as to prevent an inner circuit from being broken down by a high voltage that is caused by static electricity through the input pad 2 and the wiring 3.
The chip capacity of the input pin capacity is the sum of junction capacities between a source and a drain of the P-channel MOS transistor Pch and the N-channel MOS transistor Nch. Since the chip capacity is in proportion to the junction area of the pn junction, the input pin capacity is determined by adjusting the junction area at the stage of design.
However, when a multi-chip package is developed using chips which have the chip capacity for a single chip package, the sum of the chip capacity exceeds the upper limit of the specified chip capacity for the multi-chip package because the specified input pin capacity of the multi-chip package is the same as that of the single chip package. The chip capacity is constant so that the added capacities were unable to be changed according to the number of the chips used in the multi-chip package.